Sorry it’s quieter than ever – the weather is against me testing the GERMS filter code, so I’ve been twiddling my thumbs. I have found some odd behaviour from the IMU that’s worth sharing.
The SMPLRT_DIV register sets how often the data registers are updated, and therefore how often the data ready interrupt goes high. Normally the ADC sampling frequency is 1kHz, and the data registers are updated at a reduced frequency defined thus:
1kHz / (1 + SMPLRT_DIV)
Setting SMPLRT_DIV to 0 should give data ready interrupt (DRI) at 1kHz; 1 should product 500Hz, 2 should give 333Hz etc etc.
But what I’m seeing is that with SMPLRT_DIV <= 3, the DRI happens at 250Hz. SMPLRT_DIV >= 3 work fine producing 250Hz (3), 200Hz (4), 166Hz (5), 143Hz (6), 120Hz(7), 111Hz (8), 100Hz (9) etc etc etc. Because I’m using the DRI as the clock for the code, that means 250Hz is the fastest I can use. That’s no problem really – that’s plenty fast enough allowing 4ms per sample during which I can run the motion processing, but it’s not a limitation that’s been documented in the specs
In passing I’ve fixed a rounding error bug in the pre-flight RTF period. Not important really, but actually fixing it was what exposed the DRI frequency limit.
I’ll upload to GitHub in the next day or so once I’ve had a chance to check I’ve not broken anything.